# Trap cause = 3 (TLB miss (store) - kernel mode)



## Chitrak (Oct 3, 2010)

Hi, 

I have been investigating shared TLB mode on XLR processors such that each vCPU sees 64 entries within a core. 
The existing code base is written to support TLBs in a split mode. 
I am currently unable to boot the system up in shared mode. 
If someone has tried shared TLBs on XLR, it would be nice if you could tell me from an architectural perspective what changes need to be done to support shared TLBs. 

As I try to bring up the system, I sometimes get the following panic: 

```
PC 0x0: not in kernel
0x0+0x0 (805a813c,0,0,c6f8d000) ra 0 sz 0
pid 11, process: idle: cpu1
cpu:1-Trap cause = 3 (TLB miss (store) - kernel mode)
badvaddr = 0x805a813c, pc = 0, ra = 0x82ed0000, sr = 0x3
panic: trap
cpuid = 1
```

When I am on CPU0, I get a kernel hang just after cpu1 is initialized in smp_init_secondary().

Any help will be appreciated.

Regards
Chitrak


----------

